Faculty Directory
Jie Gu

Associate Professor of Electrical and Computer Engineering


2145 Sheridan Road
Tech Room L473
Evanston, IL 60208-3109

847-467-5854Email Jie Gu


VLSI Research Lab


Electrical and Computer Engineering


Ph.D Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN

Master of Science, Texas A&M University, College Station, TX

Bachelor of Science, Tsinghua University, Beijing, China

Research Interests

Energy Efficient Mixed-signal Computing; Machine Learning Accelerators; AI Empowered Human Machine Interface; Emerging Neuromorphic Computing Design; Novel Architecture and Circuits for Microprocessors;

Selected Publications

    Yuhao Ju, Jie Gu, A 65nm Systolic Neural CPU Processor for Combined Deep Learning and General-Purpose Computing with 95% PE Utilization, High Data Locality and Enhanced End-to-End Performance, International Conference on Solid-state Circuits (ISSCC), 2022.

    Zhengyu Chen, Xi Chen, Jie Gu, A 65nm 3T Dynamic Analog RAM Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhance, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency, International Solid-state Circuit Conference (ISSCC), 2021. 

    Yijie Wei, Kofi Otseidu, Jie Gu, Exploration of Design Space and Runtime Optimization for Affective Computing in Machine Learning Empowered Ultra-low Power SoC, Design Automation Conference (DAC), 2020.

    Yijie Wei, Qiankai Cao, Levi Hargrove, Jie Gu, A Wearable Bio-signal Processing System with Ultra-low-power SoC and Collaborative Neural Network Classifier for Low Dimensional Data Communication, International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2020.

    Tianyu Jia, Yuhao Ju, Russ Joseph, Jie Gu, NCPU: An Embedded Neural CPU Architecture on Resource-Constrained Low Power Devices for Real-time End-to-End Performance, International Symposium on Microarchitecture (MICRO), 2020.

    Tianyu Jia, Yuhao Ju, Jie Gu, A Compute-Adaptive Elastic Clock-Chain Technique with Dynamic Timing Enhancement for 2D PE-Array-Based Accelerators, International Solid-state Circuit Conference (ISSCC), 2020.

    Zhengyu Chen, Jie Gu, "A Scalable Pipelined Time-Domain DTW Engine for Time-Seres Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput", International Solid-state Circuit Conference (ISSCC), 2019.

    Tianyu Jia, Russ Joseph, Jie Gu, "An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purse Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution", International Solid-state Circuit Conference (ISSCC), 2019.

    Zhengyu Chen, Hai Zhou, Jie Gu, "Digital Compatible Synthesis, Placement and Implementation of Mixed-signal Time-domain Computing", Design Automation Conference (DAC), 2019

    Tianyu Jia, Russ Joseph, Jie Gu, “An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor”, European Solid-state Circuits Conference (ESSCIRC), 2018.

    Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph, Compiler-guided fine-grained clock adjustment for timing speculative processors, Design Automation Conference (DAC), 2018.

    Tianyu Jia, Jie Gu, A 0.3-0.86V Fully Integrated Buck Regulator with 2GHz Resonant Switching for Ultra-Low Power Applications, VLSI Symposium on Circuits, 2017.

    Tianyu Jia, Russ Joseph, Jie Gu, Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management, Design Automation Conference (DAC), 2017.

    Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu, Exploration of Associative Power Management with Instruction Governed Operation for Ultra-low Power Design, Design Automation Conference (DAC), 2016.