Faculty Directory
Jie Gu

Associate Professor of Electrical and Computer Engineering


2145 Sheridan Road
Tech Room L473
Evanston, IL 60208-3109

847-467-5854Email Jie Gu


VLSI Research Lab


Electrical and Computer Engineering


Ph.D Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN

Master of Science, Texas A&M University, College Station, TX

Bachelor of Science, Tsinghua University, Beijing, China

Research Interests

Energy Efficient Mixed-signal Computing; Machine Learning Accelerators; Emerging Neuromorphic Computing Design; Compute-adaptive Power and Clock Management with Hardware and Software Collaboration; 

Selected Publications


    Zhengyu Chen, Jie Gu, "A Scalable Pipelined Time-Domain DTW Engine for Time-Seres Classification Using Multibit Time Flip-Flops with 140Giga-Cell-Updates/s Throughput", International Solid-state Circuit Conference (ISSCC), 2019.

    Tianyu Jia, Russ Joseph, Jie Gu, "An Adaptive Clock Management Scheme Exploiting Instruction-Based Dynamic Timing Slack for a General-Purse Graphics Processor Unit with Deep Pipeline and Out-of-Order Execution", International Solid-state Circuit Conference (ISSCC), 2019.

    Zhengyu Chen, Hai Zhou, Jie Gu, "Digital Compatible Synthesis, Placement and Implementation of Mixed-signal Time-domain Computing", Design Automation Conference (DAC), 2019

    Tianyu Jia, Russ Joseph, Jie Gu, “An Instruction Driven Adaptive Clock Phase Scaling with Timing Encoding and Online Instruction Calibration for a Low Power Microprocessor”, European Solid-state Circuits Conference (ESSCIRC), 2018.

    Yuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph, Compiler-guided fine-grained clock adjustment for timing speculative processors, Design Automation Conference (DAC), 2018.

    Tianyu Jia, Jie Gu, A 0.3-0.86V Fully Integrated Buck Regulator with 2GHz Resonant Switching for Ultra-Low Power Applications, VLSI Symposium on Circuits, 2017.

    Tianyu Jia, Russ Joseph, Jie Gu, Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management, Design Automation Conference (DAC), 2017.

    Tianyu Jia, Yuanbo Fan, Russ Joseph, Jie Gu, Exploration of Associative Power Management with Instruction Governed Operation for Ultra-low Power Design, Design Automation Conference (DAC), 2016.

    Zhengyu Chen, Jie Gu, Analysis and Design of Energy Efficient Time Domain Signal Processing, International Symposium on Low Power Electronic Design (ISLPED), 2016.

    Huanyu Wang, Geng Xie, Jie Gu, Comprehensive Analysis, Modeling and Design for Hold-Timing Resiliency in Voltage Scalable Design, International Symposium on Low Power Electronic Design (ISLPED), 2016.

    Gordon Gammie, Jie Gu, et al.,  “A 28nm 0.6V low-power DSP for mobile applications”, International Solid-State Circuit Conference (ISSCC), Feb. 2011.