VLSI Research Lab Presents Two Papers at Prestigious Chip Conference ISSCC 2019

CE PhD students Tianyu Jia and Zhengyu Chen’s work demonstrates cutting-edge chip technologies at ISSCC 2019.

Tianyu Jia and Zhengyu Chen

Two computer engineering PhD students from Northwestern University’s VLSI Research Lab presented papers at the 2019 International Solid-State Circuit Conference (ISSCC), the most prestigious conference in integrated circuits (IC) chip design.

The conference, held February 17 to 21 in San Francisco, is known as the "Chip Olympics.” Only fabricated chips with state-of-art performance and strong innovation can be selected into conference publication. As a result, breakthrough chip technologies from Intel, IBM, Qualcomm, Texas Instruments, AMD, and NVIDIA, etc are typically announced at this conference.

Zhengyu Chen exhibited an accelerator chip for time series analysis used for gesture detection, voice recognition, stock prediction, and DNA sequencing, which represent one of the most challenging tasks for data mining and machine learning applications. By using specially mixed-signal time-domain computing technology, the fabricated accelerator chip offers about 1,000 times reduction on power consumption compared with conventional CPU/GPU.

Meanwhile, Tianyu Jia, presented an advanced graphics processing unit (GPU) chip with a uniquely designed, instruction-driven, ultra-dynamic clock scaling technique that leads to 30 percent energy savings on a general-purpose GPU. This technique can also be used for machine learning applications on GPU platforms, rendering a 36 percent energy saving.

The VLSI Research Lab, directed by Jie Gu, assistant professor of electrical and computer engineering, focuses on energy efficient computing with digital and mixed signal design approaches. The lab explores new computing methods for many emerging applications, including energy efficient edge computing and accelerator designs for artificial intelligence.

"It is incredible that our students can publish in this conference because it is extremely challenging for a university group to compete with large companies on producing the state-of-the-art IC chips.  Since we cannot afford the cost of building chips with the most advanced silicon technologies, e.g. 14nm or 11nm, we have to outrun our competitors with cutting-edge innovations", stated Gu.

Other news from ISSCC, included Samsung and Toshiba’s best-in-class artificial intelligence neural network accelerator chips, Intel and Qualcomm’s 5G transceiver chips, Toshiba-Western Digital’s 128-layer 3D flash memory, and Intel’s low-power robot System-on-Chip for battery-powered autonomous minibots.

VLSI Research Lab Members