COMP_ENG 387: Real-Time Digital Systems Design and Verification with FPGAs



ECE 303 (or graduate standing), ECE 355


**Graduate students interested in taking this course for Winter 2024 should enroll in COMP_ENG 495: Real-Time Digital Systems Design and Verification with FPGAs to get graduate credit. Class description can be found here.**

This course covers the systematic design of real-time digital systems and verification techniques using field-programmable gate arrays (FPGAs). The course presents a top-down design methodology, where students learn how to translate software applications in high- level level languages (such as C/C++) into SystemVerilog models for FPGA architectures. The course focuses on developing the necessary skillsets to solve real-world design challenges for high-performance computing applications, using industry-standard methodologies with an emphasis on simulation-based verification and debugging.

We will first review in detail the basic building blocks of FPGA programming with System Verilog. Second, we focus on architecture, design methodologies, best design practices, and optimization techniques to scale performance (frequency, latency, area, and power). Finally, we will cover verification methodologies, with a particular emphasis on Universal Verification Methodology (UVM), testbench development, simulation for bit-true design verification, and timing analysis.

Throughout the course students will gain real-world experience in developing applications and solving real-world design problems across some of the hottest commercial industries. The lab projects include applications in machine learning, computer vision, network packet processing, digital signal processing, and radio communications. Students will form teams to work on a final project focusing on a large scale streaming architecture, employing various strategies and techniques to optimize and measure performance


COURSE COORDINATOR: Prof. David Zaretsky

COURSE GOALS: When a student completes this course, s/he should be able to:

  • Understand the basic strategies for hardware design using SystemVerilog
  • Differentiate SystemVerilog code for hardware simulation and synthesis
  • Build a complete testbench to simulate and validate their SystemVerilog designs
  • Apply Universal Verification Methodology (UVM) for digital hardware verification
  • Use commercial CAD tools to simulate and synthesize SystemVerilog designs
  • Apply parallel processing, pipelining and streaming design methodologies to drive high-throughput performance
  • Analyze and solve timing related problems based on synthesis timing reports
  • Demonstrate a working RTL design with all aspects in the projects


·     Lecture 1: Introduction to System Verilog

·     Lecture 2: Processes, Finite State Machines

·     Lab 1: Fibonacci

·     Lecture 3: Testbenches, Simulation, Memory

·     Lecture 4: Linear Algebra, Matrices & Vector applications

·     Lab 2: Matrix Multiplication

·     Lecture 5: FIFOs, Streaming Architectures

·     Lecture 6: Image Processing Applications

·     Lab 3: Motion Detection

·     Lecture 7: Universal Verification Methodology (UVM)

·     Lecture 8: Convolutional Filter Applications

·     Lab 4: Edge Detection

·     Lecture 9: Pipelining, Loop Unrolling, Optimizations

·     Lecture 10: Network Packet Processing Applications

·     Lab 5: UDP Network Packet Protocol

·     Lecture 11: Quantization, Fixed-Point Architectures

·     Lecture 12: Digital Signal Processing Applications

·     Lab 6: Cordic

·     Lecture 13: Clock Domains, Static Timing Analysis

·     Lecture 14: Communication Systems Applications

WEEK 8-10:
·     Final Project: Streaming FM Radio

COMPUTER USAGE: Students will utilize the Synopsys Synplify Premier software for synthesis and Mentor Graphics Questasim simulation software for verification. Both software applications are available in the Wilkinson computer labs.

LABORATORY PROJECTS: This course is project oriented. Students will gain experience in software programming for hardware architectures using SystemVerilog, while applying various optimizations and design methodologies. Students will use industry standard computer-aided design tools to develop, simulate and synthesize the hardware designs. Each student will have the opportunity to design several projects individually and work in groups for the final project.

GRADES: Grading is team-based, and is composed of the following:

•      60% Weekly Labs (6)

•      30% Final Project

•      10% Class Participation


ABET CONTENT CATEGORY: 100% Engineering (Design component).