Faculty DirectoryNikos Hardavellas
Assistant Professor of Electrical Engineering and Computer Science
Contact2145 Sheridan Road
Evanston, IL 60208-3109
Email Nikos Hardavellas
Ph.D. Computer Science, Carnegie Mellon University, Pittsburgh, PA
M.S. Computer Science, Carnegie Mellon University, Pittsburgh, PA
M.S. Computer Science, University of Rochester, Rochester, NY
B.S. Computer Science, University of Crete, Heraklion, Crete, Greece
I work on Computer Architecture, primarily on techniques to enable extreme-scale multi-core processors. Such designs are elusive due to technological limitations on yield, power, and memory bandwidth. My research investigates ideas to combat "dark silicon" (i.e., our inability to power up a chip in its entirety) and pave the way to energy-efficient computing. We develop technologies that allow the underlying hardware components to be unreliable, and yet maintain the quality of the final output that the user requires. Relaxing the correctness requirement of hardware allows computations to be significantly more power efficient. At the same time, we develop technologies that eliminate the overheads of conventional computing, and turn the problem of dark silicon into an opportunity. We harness the unused chip area to build multiple heterogeneous pipelines within a core that deliver up to one order of magnitude higher power efficiency, and design novel energy-proportional nanophotonic interconnects to minimize the energy cost of data transfers. The confluence of these technologies offers significant energy improvements and minimizes energy waste, but does not eliminate the power, thermal, and bandwidth constraints of modern chips. We couple these developments with nanophotonics to design "virtual macrochips" that can deliver supercomputing power at a fraction of the energy cost and area.
Y. Demir and N. Hardavellas. Towards Energy-Efficient Photonic Interconnects. In Proceedings of SPIE, Optical Interconnects XV, San Francisco, CA, February 2015.
Y. Demir and N. Hardavellas. LaC: Integrating Laser Control in a Photonic Interconnect. In Proceedings of the IEEE Photonics Conference (IPC), pp. 28-29, La Jolla, CA, October 2014.
Y. Demir and N. Hardavellas. EcoLaser: An Adaptive Laser Control for Energy-Efficient On-Chip Photonic Interconnects. In Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), La Jolla, CA, August 2014.
Y. Demir, Y. Pan, S. Song, N. Hardavellas, G. Memik and J. Kim. Galaxy: A High-Performance Energy-Efficient Multi-Chip Architecture Using Photonic Interconnects. In Proceedings of the ACM International Conference on Supercomputing (ICS), pp. 303--312, Munich, Germany, June 2014.
M. Schuchhardt, A. Das, N. Hardavellas, G. Memik, and A. Choudhary. The Impact of Dynamic Directories on Multicore Interconnects. IEEE Computer, Special Issue on Multicore Memory Coherence, Vol. 46(10), October 2013.
N. Hardavellas. The Rise and Fall of Dark Silicon. USENIX ;login:, Vol. 37, No. 2, pp. 7-17, April 2012. Invited Paper.
A. Das, M. Schuchhardt, N. Hardavellas, G. Memik, and A. Choudhary. Dynamic Directories: Reducing On-Chip Interconnect Power in Multicores. In Proceedings of Design, Automation, and Test in Europe (DATE), Dresden, Germany, March 2012.
N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki. Toward Dark Silicon in Servers. In IEEE Micro, Special Issue on Big Chips, Vol. 31(4), pp. 6-15, July/August 2011. IEEE Micro Spotlight Paper,February 2012.
S. Liu, B. Leung, A. Neckar, S. Ogrenci-Memik, G. Memik, and N. Hardavellas. Hardware/Software Techniques for DRAM Thermal Management. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA), San Antonio, TX, February 2011.
N. Hardavellas, M. Ferdman, B. Falsafi and A. Ailamaki. Near-Optimal Cache Block Placement with Reactive Nonuniform Cache Architectures. IEEE Micro, Vol. 30(1), pp. 20-28, January/February 2010. IEEE Micro Top Picks from Computer Architecture Conferences.
I. Pandis, R. Johnson, N. Hardavellas and A. Ailamaki. Data-Oriented Transaction Execution. In Proceedings of the VLDB Endowment (PVLDB), Vol. 3(1), pp. 928-939, August 2010.
N. Hardavellas, M. Ferdman, B. Falsafi and A. Ailamaki. Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches. In Proceedings of the 36th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pp. 184–195, Austin, TX, June 2009.
R. Johnson, I. Pandis, N. Hardavellas, A. Ailamaki, and B. Falsafi. Shore-MT: A Scalable Storage Manager for the Multicore Era. In Proceedings of the 12th International Conference on Extending Database Technology (EDBT), pp. 24–35, Saint-Petersburg, Russia, March 2009.
J. Kim, N. Hardavellas, K. Mai, B. Falsafi, and J. C. Hoe. Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. In Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), pp. 197–209, Chicago, IL, December 2007.
R. Johnson, N. Hardavellas, I. Pandis, N. Mancheril, S. Harizopoulos, K. Sabirli, A. Ailamaki, and B. Falsafi. To Share Or Not To Share? In Proceedings of the 33rd International Conference on Very Large Data Bases (VLDB), pp. 351–362, Vienna, Austria, September 2007.
S. Chen, P. B. Gibbons, M. Kozuch, V. Liaskovitis, A. Ailamaki, G. E. Blelloch, B. Falsafi, L. Fix, N. Hardavellas, T. C. Mowry, and C. Wilkerson. Scheduling Threads for Constructive Cache Sharing on CMPs. In Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures (SPAA), pp. 105–115, San Diego, CA, June 2007.
N. Hardavellas, I. Pandis, R. Johnson, N. Mancheril, A. Ailamaki, and B. Falsafi. Database Servers on Chip Multiprocessors: Limitations and Opportunities. In Proceedigs offf the 3rd Biennial Conference on Innovative Data Systems Research (CIDR), pp. 79–87, Asilomar, CA, January 2007.
D. Dash, K. Gao, N. Hardavellas, S. Harizopoulos, R. Johnson, N. Mancheril, I. Pandis, V. Shkapenyuk, and A. Ailamaki. Simultaneous Pipelining in QPipe: Exploiting Work Sharing Opportunities Across Queries. In Proceedingsof the 22nd International Conference on Data Engineering (ICDE), Atlanta, GA, April 2006. Best Demonstration Award
T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, C. Gniady, A. Ailamaki, and B. Falsafi. Store-Ordered Streaming of Shared Memory. In Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT), pp. 75–86, Saint Louis, MO, September 2005.
T. F. Wenisch, S. Somogyi, N. Hardavellas, J. Kim, A. Ailamaki, and B. Falsafi. Temporal Streaming of Shared Memory. In Proceedings of the 32nd ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pp. 222–233, Madison, WI, June 2005.
N. Hardavellas, S. Somogyi, T. F. Wenisch, R. E. Wunderlich, S. Chen, J. Kim, B. Falsafi, J. C. Hoe, and A. Nowatzyk. SimFlex: a Fast, Accurate, Flexible Full-System Simulation Framework for Performance Evaluation of Server Architecture. ACM SIGMETRICS Performance Evaluation Review (PER) Special Issue on Tools for Computer Architecture Research, Vol. 31(4), pp. 31–35, March 2004
S. Dwarkadas, N. Hardavellas, L. Kontothanassis, R. Nikhil, and R. Stets. Cashmere-VLM: Remote Memory Paging for Software Distributed Shared Memory. In Proceedings of the 13th IEEE/ACM International Parallel Processing Symposium (IPPS), pp. 153–159, San Juan, Puerto Rico, April 1999.
R. J. Stets, S. Dwarkadas, N. Hardavellas, G. C. Hunt, L. Kontothanassis, S. Parthasarathy, and M. L. Scott. Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network. In Proceedings of the 16th ACM Symposium on Operating Systems Principles (SOSP), pp. 170–183, Saint Malo, France, October 1997.
L. Kontothanassis, G. C. Hunt, R. J. Stets, N. Hardavellas, M. Cierniak, S. Parthasarathy, W. Meira Jr., S. Dwarkadas, and M. L. Scott. VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks. In Proceedings of the 24th ACM/IEEE Annual International Symposium on Computer Architecture (ISCA), pp. 157–169, Denver, CO, June 1997