Faculty Directory
Hai Zhou

Associate Professor of Electrical Engineering and Computer Science

Contact

2145 Sheridan Road
Tech Room L461
Evanston, IL 60208-3109

847-491-4155Email Hai Zhou

Website

Hai Zhou's Homepage

Center for Ultra Scale Computing and Information Security (CUCIS)


Departments

Electrical Engineering and Computer Science


Download CV

Education

Ph.D. Computer Science, University of Texas, Austin, TX

M.E. Computer Science and Technology, Tsinghua University, Beijing, China

B.E. Computer Science and Technology, Tsinghua University, Beijing, China


Research Interests

Algorithm design; formal methods and their applications to VLSI CAD; security


Selected Publications

    H. Zhou and D. F. Wong. Global Routing with Crosstalk Constraints. IEEE Transactions on Computer-Aided Design, 18(11), pp. 1683-1688, November, 1999. 

    H. Zhou, D. F. Wong, I-M. Liu, and A. Aziz. Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations. IEEE Transactions on Computer-Aided Design, 19(7), pp. 819-824, July, 2000. 

    A. Goel, K. Sa jid, H. Zhou, A. Aziz, and V. Singhal. BDD-based Procedures for a Theory of Equality with Uninterpreted Functions. Journal of Formal Methods in System Design, 22(3), pp. 205-224, May 2003. 

    H. Zhou. Timing Analysis with Crosstalk is a Fixpoint on a Complete Lattice. IEEE Transactions on Computer-Aided Design, 22(9), pp. 1261-1269, Sept. 2003. (IEEE Donald O. Pederson Award finalist)

    H. Zhou. Efficient Steiner Tree Construction Based on Spanning Graphs. IEEE Transactions on Computer-Aided Design, 23(5), pp. 704-710, May 2004. 

    H. Zhou and C. Lin, Retiming for Wire Pipelining in System-On-Chip. IEEE Transactions on Computer-Aided Design, 23(9), pp. 1338-1345, Sept. 2004. 

    D. Sinha, N. Shenoy, and H. Zhou, Statistical Timing Yield Optimization by Gate Sizing. IEEE Transactions on VLSI Systems. 14(10), Oct. 2006. 

    H. Zhou. A New Efficient Retiming Algorithm Derived by Formal Manipulation. ACM Transactions on Design Automation of Electronic Systems. 13(1). Article No. 7. Jan. 2008.

    Y. Lu, H. Zhou, L. Shang, and X. Zeng. Multicore Parallelization of Min-Cost Flow for CAD Applications. IEEE Transactions on Computer-Aided Design. 29(10), pp. 1546-1557, Oct. 2010.

    C. Feng, H. Zhou, C. Yan, J. Tao, and X. Zeng. Efficient Approximation Algorithms for CMP Dummy Fill. IEEE Transactions on Computer-Aided Design. 30(3), pp. 402-415, Mar. 2011. 

    Q. Ma, Z. Qian, E. F.Y. Young, and H. Zhou. MSV-Driven Floorplanning. IEEE Transactions on Computer-Aided Design. 30(8), pp. 1152-1162, Aug. 2011.