EECS 355: Asic and FPGA Design

Quarter Offered

Fall : 3:30-4:50 TuTh ; Zaretsky


EECS 303 or equivalent.


Overview of Computer Aided Design tool flow for ASIC and FPGA Design. Synthesis from hardware description languages and creation of finite state machines. Differences between FPGA and ASIC design flows. Exploration of concepts in several projects.

RECOMMENDED TEXTBOOKS: Nazeih M. Botros, HDL Programming Fundamentals VHDL and Verilog, Da Vinci Engineering Press/Thomson Delmar Learning/p>

REFERENCE TEXTS: Course handouts

COURSE INSTRUCTOR: David C. Zaretsky (

COURSE GOALS: To introduce students to the process of designing application specific hardware implementations of algorithms for ASICs and FPGAs. Students will work with commercial computer aided design tools to synthesize designs described in hardware description languages. Topics covered will include differences between hardware description languages for synthesis and simulation, behavioral synthesis, gate-level design, register transfer level design, design methodologies, finite state machines, design reuse and intellectual property cores, and optimization.

PRE-REQUISITES : EECS 303 or equivalent.


Week 1 : Overview of VHDL. Introduce synthesis and subset.
Week 2: Continue discussion synthesis subset. Review finite state machines.
Week 3-4: Introduce ASIC design methodologies and synthesis tools, VHDL simulation and verification
Week 5: Discuss standard libraries. Introduce optimizations
Week 6-7: Introduce FPGA Synthesis tools and Intellectual Property Cores
Week 8-10: Topics TBA, related to main project.

COMPUTER USAGE: Students will be expected to be comfortable with Sun/UNIX platform to run and manage Computer Aided Design projects with synthesis tools.

LABORATORY PROJECTS: Course is project oriented. Students will gain experience writing hardware designs in VHDL using several different styles (including behavioral, gate level design and Register Transfer Level Design). They will use industry standard computer-aided design tools including tools from Synopsys, Cadence, Synplicity, and Xilinx. They will target commercially viable standard libraries to create physical layout of ASICs and work with industry standard FPGAs from Xilinx. Each student will have the opportunity to design several projects individually and work in groups to create larger designs.

GRADES: Grades will be 100% project based

COURSE OBJECTIVES: When a student completes this course, s/he should be able to:

1. Have an understanding of the difference between VHDL code for hardware simulation and hardware synthesis.

2. Understand the basic strategies for hardware design using VHDL.

3. Understand and critically compare state-of-the-art design automation methodologies.

4. Use computer aided design tools to physically synthesize a design written in VHDL and generate a physical layout for testing and fabrication.

5. Use computer aided design tools to synthesize a design written in VHDL and generate a bitstream for execution on an FPGA.

6. Write intelligent VHDL designs that show understanding of basic hardware that will be synthesized with tools.

7. Verify hardware designs at several levels in the design flow.

8. Understand the need for and application of different optimization techniques, and their relative interaction within computer aided design tools.

9. Take advantage of pre-existing intellectual property to reduce design time and produce more optimal results.