With the slowdown of processor scaling, general-purpose platforms such as CPUs are no longer sufficient to meet the computing power demands of rapidly evolving applications. Domain-specific accelerators become the key to unlocking hardware potential for enhanced performance and energy efficiency. In this talk, I will introduce our work on accelerator architecture design with emerging resistive random-access memory (ReRAM) for future computing needs, including architectures for deep learning, graph processing, and scientific computing. Then, I will discuss accelerator design on high-bandwidth memory (HBM) FPGA platforms for deployment in frontier computing systems, highlighting how we make FPGA accelerators competitive with GPUs. Our focus will be on the design and prototyping of sparse accelerators using Xilinx HBM FPGA platforms. Additionally, I will discuss a practical application of accelerators in industry software: FPGA-accelerated ANSYS LS-DYNA. To conclude, I will share my visions for the future of accelerator architecture and systems.